Our story...

In late 2022, the Mark Evison Foundation delivered a presentation in our school where they described their wishes to help young people bring out the best in themselves. It was this presentation and the promise of funding which gave several groups, including us, the motivation to begin working on projects of significant complexity.

Our first step in this project was to create a rough table of costs based around a set of initial requirements, including our main goal of creating an 8-bit CPU. This yielded an initial budget of £330, which after discussion with the MEF, was deemed too expensive. As a result, we decided to reduce the capability of our CPU to 4-bits, which in turn led to our budget being reduced to £230.

We then began to design a high-level schematic in diagrams.net. This illustrated the standard fetch-decode-execute cycle, as well as our own memory and output sections. It was at this stage that we created the Mk-λ’s instruction set. A typical 4-bit CPU would allow for 16 different instructions, however, we made use of a clever trick to extend this to 19 different instructions. These include simple arithmetic and logic operations, branching operations, as well as operations to interface with memory and allow for subroutines to be created. The final design was a Harvard Architecture CPU, featuring separate memory stores for instructions and data.

We submitted our proposal to the MEF and continued to work on the high-level schematic up until our in-person judging session in February; this led to our project being approved. After this, we started to work on a low-level schematic to accurately simulate how our CPU would function. This was comprised entirely of logic gates, and, being created in Digital, we were able to test it actively throughout its creation. This was a lengthy process which posed many technical challenges, taking over two months in itself to complete.

Once the low-level schematic was complete, we began to create a breadboard-level schematic to determine the physical layout of the CPU. Here, we decided how best to place wires and chips onto the breadboards so as to minimise our project’s total cost and maximise the CPU’s overall efficiency. This phase brought challenges of its own, such as the need to group logic gates together as they would be on physical chips. Complications with running simulations in Digtial during this phase were also encountered, many of which took hours to rectify. This, among other issues, made this part of our design take the longest to complete.

After this, we set out on a hunt for the components needed to make our CPU a reality. Whilst we already had a rough table of costs at this point, our design allowed us to update the quantity of each component in preparation for funding from the MEF. To our dismay, our new total cost exceeded our proposed budget, meaning that we needed to request an additional £30. The MEF agreed with our revised budged and gladly provided us with the funds necessary. Soon after, we began making our first purchase, with the intention of making a second order after the breadboard-level schematic’s completion. This purchase included half of the components necessary to build the Mk-λ.

With the instruction set and low-level design complete, we created an assembly language, along with an assembler which we call the Lambdassembler. The assembler allows us to write programs in a human-friendly way, thereby making programming easier.

In trying to stick to deadlines set by ourselves, and to distribute work effectively, we decided it would be best to start the construction phase of our project whilst the breadboard-level schematic was still underway. We began to build the simpler constituents of our CPU, namely those which had already been designed, followed by increasingly more complex components as the design of the schematic progressed. Where appropriate, we made sure to test each component independently, thereby allowing us to isolate each problem to a specific part of the CPU.

Although following an iterative testing process as described above would have been ideal, this was not always possible. As our CPU grew, the number of dependencies between components also grew, making it necessary to test several components together at once. This made the challenge of identifying any misaligned, loose or missing wires significantly more difficult and time consuming.

To aid the testing process, we wrote software to run through a vast quantity of tests on the physical CPU in a similar fashion to those performed in Digital. This brought the time it took to solve each issue from, on average, 6 hours to 2 hours.

Although we intended to follow the breadboard-level schematic whilst building the CPU, we did make a number of optimisations to the schematic along the way, some of which were due to mistakes made during construction. For example, orienting each breadboard and chip correctly was something we had to pay close attention to.

All in all, we spent about 260 hours building and testing the MEF Mk-λ. If you wish to support the Mark Evison Foundation's cause, we ask that you consider donating to their charity here. Thank you.